Maxim-integrated 73M1866B/73M1966B Implementers Guide Uživatelský manuál Strana 1

Simplifying System IntegrationTM 73M1866B/73M1966B Implementer’s Guide March 26, 2010 Rev. 1.3 UG_1

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 10 Rev. 1.3 3.2 Line-Side Device (73M1916) Configuration The Line-side device setup includes th

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 11 Barrier SyncSYNL == 0?SLHS == 1?SLEEP = 1Wait 200 msSLEEP = 0EndNoNoNoYesYesYesResto

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 12 Rev. 1.3 Begin : RESYNC 1. IF CNT1 !=1 goto 8 2. Write RSTLSBI = 1 (RG0D = xxxx_1xxx). 3.

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 13 3.2.2 Receiver DC Offset Calibration The effect of residual DC offset caused by the

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 14 Rev. 1.3 Receiver DC Offset CalibrationOFH == 0?ENDC = ENVLD = ENDT = 0ENAC = ENFEL = 1 THE

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 15 3.2.3 Initial Line State Configuration The default condition of the device is to be

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 16 Rev. 1.3 Initial Line State ConfigurationENAPOL = 1ENSYNL = 1ENFEL = 1OFH = ENDC = ENAC =

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 17 4 On-Hook Procedures The on-hook procedures described in this section include: •

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 18 Rev. 1.3 4.2 Off-Hook Request The registers used in the off-hook request procedure are: 0x

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 19 Off-Hook RequestRXBST =0EndTHEN =1ENNOM =0TXEN = RXEN = ATEN =1 OFH = 1

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 2 Rev. 1.3 © 2010 Teridian Semiconductor Corporation.

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 20 Rev. 1.3 4.3 Ring Detection and Line Voltage Reversal When the 73M1966 is in on-hook mode, a

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 21 The registers used for Ring Detection and Line Voltage Reversal are: 0x05 ENGPIO7

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 22 Rev. 1.3 4.4 Line-in-use and Loss of Battery Feed When the FXO line is in the on-hook mode,

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 23 5 Off-Hook Procedures The off-hook procedures described in this section include: •

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 24 Rev. 1.3 6 Interrupt Processing During the course of operation the 73M1x66 can be expected t

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 25 6.2 PCLKDT Interrupt The triggering of the PCLKDT interrupt indicates that the devi

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 26 Rev. 1.3 6.4 SYNL Interrupt The triggering of the SYNL interrupt indicates that the device h

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 27 7 Register Summary Address (hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 28 Rev. 1.3 8 Related Documentation The following 73M1x66B documents are available from Teridi

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 29 Revision History Revision Date Description 1.0 5/21/2009 First publication. 1.1

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 3 Table of Contents 1 Introduction ...

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 4 Rev. 1.3 1 Introduction This guide describes how to use the 73M1866B and 73M1966B MicroDAA® F

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 5 2 Hardware Requirements 2.1 Reset The reset pin of the 73M1x66B is active low. Fo

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 6 Rev. 1.3 3 Device Configuration and Initialization 3.1 Host-Side Device (73M1906B) Configura

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 7 3.1.2 PCLK Clock Recovery and PLL Lock Detection The 73M1x66B requires that the PLL

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 8 Rev. 1.3 3.1.3 Call Progress Monitor Reset If used in 16 kHz mode, the call progress monitor

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Rev. 1.3 9 3.1.4 PCM Interface Configuration The PCM Highway Interface is described in Section