Maxim-integrated DS4830 Optical Microcontroller Uživatelský manuál Strana 133
- Strana / 227
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
DS4830 User’s Guide
133
15.5 – GPIO Port 6 Register Descriptions
Port 6 provides seven GPIO pins that are multiplexed with the test access port (TAP), DAC, Sample trigger input, PWM
and ADC. ADC function is enabled when PINSEL.n is set to ‘1’ (where n = 4, 5, 10 or 11). Single or Differential ADC
mode is selected by ADDATA.DIFF bit during ADC configuration (when ADCN.CFG is set to ‘1’). DAC function is enabled
when DACCFG.n is set to either “10b” or “01b” (where n = 2 or 6). PWM is enabled when corresponding PWM local
enable and PWM master enable is set to ‘1’.
On device reset, the TAP port is active, allowing for in-circuit debugging and programming. The JTAG is active by default
on Port6.0-3 and it is disabled when SC.TAP bit is set to ‘0’. Enabled special functions operate on the JTAG ports only if
SC.TAP bit is set to ‘0’. Port 6 also provides GPIO interrupts on all of the pins. The GPIO works only when SC.TAP = 0. A
GPIO interrupt can be generated when the pin is being operated as a GPIO, or a special or alternate function. Three
additional registers, EIF6, EIE6, and EIES6 are used to control the GPIO interrupts. Port6.7 is not present in the Port6.
15.5.1 – GPIO Direction Register Port 6 (PD6)
Bit #
7
6
5
4
3
2
1
0
Name
Reserved
PD6_6
PD6_5
PD6_4
PD6_3
PD6_2
PD6_1
PD6_0
Reset
0
0
0
0
0
0
0
0
Access
r
rw
rw
rw
rw
rw
rw
rw
PD6 is an 8-bit register used to determine the direction of the pins when they are used as GPIO pins. Each pin is
independently controlled by its direction bit. When PD6.n (n = 0 to 6) is set to 1, the pin is an output; data in the PO6.n bit
will be driven on the pin. When PD6.n is cleared to 0, the pin is an input, and allows an external signal to drive the pin.
The P channel pull-up transistor is controlled by the PO6.n bit. If PO6.n is set to 1, the corresponding weak pull-up is
turned on, if the PO6.n bit is cleared to 0, the weak pull-up is turned off and the pin’s input is high-impedance.
15.5.2 – GPIO Output Register Port 6 (PO6)
Bit #
7
6
5
4
3
2
1
0
Name
Reserved
PO6_6
PO6_5
PO6_4
PO6_3
PO6_2
PO6_1
PO6_0
Reset
1
1
1
1
1
1
1
1
Access
r
rw
rw
rw
rw
rw
rw
rw
PO6 is an 8-bit register that controls the output data of a GPIO pin. If the pin is setup to be an output (PD6.n = 1), the
data in PO6.n will be output on the pin. If the pin is set as an input (PD6.n = 0), setting PO6.n to a 1 enables a p-channel
weak pull-up, otherwise the pin’s input is high impedance.
15.5.3 – GPIO Input Register for Port 6 (PI6)
Bit #
7
6
5
4
3
2
1
0
Name
Reserved
PI6_6
PI6_5
PI6_4
PI6_3
PI6_2
PI6_1
PI6_0
Reset
1
s
s
s
s
s
s
s
Access
r
r
r
r
r
r
r
r
PI6 is an 8-bit register which contains the data that is applied to the GPIO pins. The PI6 input register contains valid input
data even when the pin is not operating as GPIO. The reset value for this register is dependent on the logical states
applied to the pins. Note that each pin has a weak pull-up circuit when functioning as an input and the P channel pull-up
transistor is controlled by the PO6.n bit.
15.5.4 – GPIO Port 6 External Interrupt Edge Select Register (EIES6)
Bit #
7
6
5
4
3
2
1
0
Name
Reserved
IT6
IT5
IT4
IT3
IT2
IT1
IT0
Reset
0
0
0
0
0
0
0
0
Access
r
rw
rw
rw
rw
rw
rw
rw
The EIES6 register sets the interrupt edge select to trigger an interrupt on either a rising or falling edge. Setting the
IESP6_n bits to ‘0’ will trigger the corresponding interrupt on a positive edge. When these bits are set to a ‘1’, the
interrupt will be on a negative edge.
- OpticalMicrocontroller 1
- User’sGuide 1
- Contents 2
- SECTION 1 – OVERVIEW 9
- DS4830 User’s Guide 10
- SECTION 2 – ARCHITECTURE 11
- 2.2 – Register Space 12
- 2.3 – Memory Types 13
- 2.5 – Data Alignment 20
- 2.6 – Reset Conditions 20
- 2.7 – Clock Generation 22
- SECTION 5 – INTERRUPTS 36
- 5.1 – Servicing Interrupts 37
- 6.1 – Detailed Description 42
- 6.3 – DAC Code Examples 45
- 7.1 – Detailed Description 46
- 7.3 – ADC Code Examples 58
- SECTION 8 – SAMPLE AND HOLD 60
- 9.1 – Detailed Description 68
- SECTION 10 – I 76
- SECTION 11 – I 89
- C-COMPATIBLE SLAVE INTERFACE 89
- 11.1 – Detailed Description 90
- 12.2 – SPI System Errors 101
- 12.3 – SPI Interrupts 102
- SECTION 13 – 3-WIRE 110
- Using PWMCN and PWMDATA 113
- Core Clock 120
- FrequencyClockPWM 123
- FrequencyFramePWM 123
- * = 01b 127
- MULTIPLIER 140
- SECTION 19 – WATCHDOG TIMER 146
- 20.1 – TAP Controller 150
- 20.2 – TAP State Control 151
- 20.3 – Communication via TAP 152
- 21.2 – Debug Mode 160
- 22.1 – Detailed Description 169
- 22.2 – Bootloader Operation 171
- 22.3 – Bootloader Commands 173
- SECTION 23 – PROGRAMMING 179
- SECTION 24 – INSTRUCTION SET 192
- SECTION 25 – UTILITY ROM 220
- 25.4 – Utility ROM Examples 227
Související produkty a manuály pro Hardware Maxim-integrated DS4830 Optical Microcontroller
(76 stránky)© 2020, manymanuals.cz. Všechna práva vyhrazena. | 0.224 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentáře k této Příručce