Maxim-integrated High-Speed Microcontroller Users Guide: Network Mi Uživatelský manuál

Functional DiagramsPin Configurations appear at end of data sheet.Functional Diagrams continued at end of data sheet.UCSP is a trademark of Maxim Inte

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement10Exported RAM Functions . . . . . . . . . . . . . . . . . . . . . . . . . .

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement100External Memory AccessThe DS80C400 follows the memory interface convention

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement101Table 6-3. Extended Address Generation 1Only 32kB of memory is accessible

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement102Table 6-6 illustrates how program memory is segmented based on the setting

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement103Figure 6-4. Multiplexed Address/Data BusDS80C400P7.3/A3P7.4/A4P7.5/A5P7.6/

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement104DS80C400P7.3/A3P7.4/A4P7.5/A5P7.6/A6P7.7/A7Vcc1EA\ALEPSEN\P2.0\A8P2.1\A9P2

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement105CE0 =4Mx8PCE0 =1Mx8PCE1 =1Mx8PCE2 =1Mx8PCE3 =1Mx8CE1 =4Mx8CE3=4Mx8CE2 =4Mx

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement106CE0 = 32kB x 8PCE0 = 32kB x 8PCE1 = 32kB x 8PCE2 = 32kB x 8PCE3 = 32kB x 8

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement107CE0 =512kB x 8Non-AddressableNon-AddressablePCE0 =1MB x 8PCE1 =1MB x 8Non-

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement108Write-Protection Feature (DS80C400 Only)When combined program/data memory

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement109(TSL: DPS.5) is set to 1, the SEL bit (DPS.0) is automatically toggled eve

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement11Figure 5-1. System Clock Control Diagram . . . . . . . . . . . . . . . . .

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement110Early Warning Power-Fail InterruptThe PFI status bit is set if either VCC1

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement111SwitchbackIn addition to the switchback sources listed in the High-Speed M

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement112Power-On/Power-Fail ResetThe DS80C400 incorporates an internal voltage ref

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement113Reset OutputsThe microcontroller has one reset output, the RSTOL pin.Reset

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement114INT51-WIRE EOWMIFLAGBITS1-WIRE INTERRUPTENABLE BITSTBEOW_LOWOW_SHORTRSRFR

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement115EOWMIINTERRUPTENABLE BITSFLAGBITSINTERRUPTPRIORITY BITSINTERRUPTSELECTIONH

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement116ADDENDUM TO SECTION 10: PARALLEL I/OChanges to this section primarily invo

5V-Tolerant I/OIn order for the DS80C400 to provide 5V-tolerant I/O, additional circuitry has been incorporated to detect I/O pad voltages that exceed

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement118ADDENDUM TO SECTION 11: PROGRAMMABLE TIMERSThe timers of the DS80C400 are

Figure 11-2. Timers/Counters 0, 1, and 3, Mode 2 Figure 11-3. Timer/Counter 0, Mode 3 High-Speed Microcontroller User’sGuide: Network MicrocontrollerS

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement12Figure 19-6. Intermission . . . . . . . . . . . . . . . . . . . . . . . .

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement120Figure 11-4. Timer/Counter 2 Clock-Out Mode Figure 11-5. Timer/Counter 2 B

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement121Figure 11-6. Tiimer/Counter 2 Autoreload Mode, DCEN = 0 Figure 11-7. Timer

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement122Figure 11-8. Timer/Counter 2 with Optional CaptureDivide-by-13 OptionAnoth

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement123ference but allows the use of a crystal frequency that is acceptable for s

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement124ADDENDUM TO SECTION 12: SERIAL I/OThe DS80C400 high-speed microcontroller

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement125Mode 0Mode 0 is synchronous, so the shift clock output frequency is the ba

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement126Mode 2In this asynchronous mode, baud rates are always derived from the os

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement127Using Timer 1 or Timer 3 for Baud-Rate GenerationThe following text and Ta

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement128Table 12-6. Relationship Between External Crystal Frequency and Timer 2Whe

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement129ADDENDUM TO SECTION 13: TIMED-ACCESS PROTECTIONA number of timed-access-pr

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement13LIST OF TABLESTable 5-1. System Clock Configuration . . . . . . . . . . .

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement130ADDENDUM TO SECTION 16: INSTRUCTION SET DETAILSThe DS80C400 supports one o

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement131The DS80C400 supports interrupts from any location in the 24-bit address f

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement13224-Bit Contiguous Addressing ModeWhen the AM1 bit is set, the DS80C400 ope

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement133SECTION 17: TROUBLESHOOTINGSoftware Breakpoint ModeThe DS80C400 provides

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement134Figure 17-1. Force Feeding a Breakpoint During An Instruction Other Than M

ADDENDUM TO SECTION 18: MICROCONTROLLER DEVELOPMENTSUPPORTRefer to the High-Speed Microcontroller User’s Guide.High-Speed Microcontroller User’sGuide:

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement136SECTION 19: CONTROLLER AREA NETWORK (CAN) MODULEThe DS80C400 and DS80C410

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement137MOVX MESSAGE CENTERS FOR CAN 0CAN 0 CONTROL/STATUS/MASK REGISTERSREGISTER7

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement1381The first 2 bytes of the CAN 0 MOVX memory address are dependent on the s

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement139CAN 0 Media ID Mask Register 0 (C0MID0)MOVX Address17 6543210xxxx00hCAN 0

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement14ADDENDUM TO SECTION 1: INTRODUCTION The DS80C400 is the third-generation mi

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement140SJW1, SJW0Bits 7–6CAN synchronization jump width select. These bits specif

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement141SMPBit 7TSEG26–24Bits 6–4CAN sampling rate. The sampling rate (SMP) bit de

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement142CAN 0 Standard Global Mask Register 0 (C0SGM0)MOVX Address176543210xxxx06h

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement143CAN 0 Extended Global Mask Register 3 (C0EGM3)MOVX Address17 6543210xxxx0B

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement144CAN 0 Message Center 15 Mask Register 3 (C0M15M3)MOVX Address176543210xxxx

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement145CAN 0 Message Center y Arbitration Register 3 (C0MyAR3)ID28–ID0Bits 2–1(C0

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement146CAN 0 Message Center y Format Register (C0MyF)MOVX Address176543210Xxxxy6h

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement147CAN 0 Message Center y Data Byte 0 (C0MyD0)CAN 0 Message Center y Data Byt

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement148Frame TypesThe CAN 2.0B protocol specifies two different message formats,

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement149Control field: (Standard and extended format) The control field is made up

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement15DeviceNet is a trademark of OpenDeviceNet Vendor Association Inc.16 interru

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement150Figure 19-5. Acknowledge FieldEnd of frame: (Standard and extended format)

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement151Error frame: The error frame is transmitted by a CAN controller when the C

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement152The error counters are not incremented as a result of condition 3. The CAN

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement153Figure 19-10. CAN Interrupt LogicArbitration/Masking ConsiderationsThe CAN

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement154(C0SGM0–1) when EX/ST = 0, or the extended global mask registers (C0EGM0–3

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement155Receiving Data MessagesEach incoming data message is compared sequentially

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement156If software wants to modify the data in a message center configured for tr

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement157Case 3: Software-initiated reply. (Reply through same message center, usi

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement158Remote Frame Handling in Relation to the DTBYC BitsThe DTBYC bits function

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement159Case 1: WTOE = 1 (Overwrites allowed)1. Software configures message center

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement16The DS80C400 supports one of three different addressing modes, as selected

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement160The theory behind the CAN autobaud feature is relatively simple. If a CAN

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement161Bus-Off/Bus-Off Recovery and Error Counter OperationThe CAN module contain

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement162Bit TimingBit timing in the CAN 2.0B specification is based on a unit call

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement163The timing of the various time segments is determined by using the followi

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement164Bus Rate Timing ExampleThe following table shows a few example bit timing

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement165SECTION 20: ARITHMETIC ACCELERATORThe DS80C400 incorporates an arithmetic

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement166Divide (32-bit by 16-bit or 16-bit by 16-bit)The divide operation utilizes

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement1676. Poll the MST bit until cleared (for nine machine cycles).7. Read MA for

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement168SECTION 21: 1-WIRE BUS MASTERThe 1-Wire master contained within the DS80C4

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement169SETTING UP THE 1-WIRE MASTERThe first step is to determine the input cryst

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement17Register MapThe register map is separate from the program and data memory a

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement170MOV OWMDR, #0AAh ; Load up the byte to be transmitLCALL Wait4int ; Loop un

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement171Table 21-2. Transmit/Receive Byte Sequencern= decision discrepancy data (w

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement1729. Since the most significant discrepancy (d2) did not change, the next hi

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement173Figure 22-1. Ethernet Controller Block DiagramAssigning a Physical MAC Add

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement174Table 22-2. MAC Control Register Bit Summary MEDIA INDEPENDENT INTERFACE (

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement175Figure 22-2. MII Signal DiagramFigure 22-3. MII Mode–Byte/Bit Transmit and

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement176ENDEC MODE—HEARTBEAT SIGNAL QUALITY GENERATORWhen operating in ENDEC mode,

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement177For reception, the MAC automatically synchronizes on the preamble and star

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement178DEFERRAL CHECKWhen a transmit request is queued, the MAC monitors the CRS

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement179Figure 22-7. Half-Duplex Transmit Deferral/Collision Handling FLOW CONTROL

Special-Function Register MapSpecial-Function Register LocationHigh-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement18STARTADDRESS

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement180The MAC also can transmit a pause control frame on the request from the ap

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement181Figure 22-9. External Loopback Mode (MAC Control OM1:0 = 10b) ADDRESS FILT

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement182One way to prevent receive packets from always being stored to the receive

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement183Figure 22-10. Example 8kB Data Memory Partition...Page 31Page 6Page

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement184TRANSMIT/RECEIVE DATA BUFFER WORD ORIENTATION: ENDIANESSThe big/little-end

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement185Figure 22-12. Transmit Flow Diagram CPULoad transmit data buffer memory (M

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement186RECEIVING DATAAfter configuring the Ethernet MAC and the defining the rece

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement187USING WAKE-UP FRAMESAs discussed in the DS80C400 data sheet, the Ethernet

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement1881. CSR write register (CSRA = 28h, CSRD = 00_00_00_73h) Filter 0 byte mask

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement189SECTION 23: EMBEDDED DS80C400 SILICON SOFTWAREThe DS80C400 silicon softwar

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement19Special-Function Register Location (continued)REGISTERBIT 7 BIT 6 BIT 5 BIT

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement190D [begin address [length]]Dumps the selected memory range from the current

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement191UTILITY FUNCTIONScrc16Description: int crc16(int crc, /* initial CRC valu

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement192mem_compareDescription: int mem_compare(void *block0, /* pointer to the st

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement193getpseudorandomDescription: unsigned char getpseudorandom(void);The getpse

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement194rom_malloc_dirtyDescription: void rom_malloc_dirty(int blocksize); /* requ

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement195SOCKET FUNCTION CALLING CONVENTIONSThe DS80C400 silicon software socket fu

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement196SOCKET FUNCTIONS/POINTERSPARAMBUFFERThe DS80C400 silicon software exports

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement197recvfromDescription: int recvfrom(int s, /* receive on socket with handle

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement198listenDescription: int listen(int s, /* socket on which to listen for conn

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement199sendDescription: int send(int s, /* socket on which to send data */void *b

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement2TABLE OF CONTENTSADDENDUM TO SECTION 1: INTRODUCTION 14Features . . . . .

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement20REGISTERBIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0ADDRESSRCAP2L CAhRCA

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement200getsocknameDescription: int getsockname(int s, /* socket for which to get

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement201join/leaveDescriptions: int join(int s, /* socket to add to the multicast

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement202getipv6paramsDescriptions: getipv6params(void *parameters); /* pointer to

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement203DHCP FUNCTIONSdhcp_initDescription: int dhcp_init(void);The dhcp_init func

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement204dhcp_stopDescription: void dhcp_stop(void);The dhcp_stop function disables

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement205tftp_nextDescription: int tftp_next(int ack_only); /* flag to signal when

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement206task_getpriorityDescription: int task_getpriority(int id); /* id of the ta

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement207task_killDescription: int task_kill(int id); /* id of the task to be kille

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement208task_signalDescription: int task_signal(int id, /* id of task to send sign

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement209rom_task_switch_outThe rom_task_switch_out function is called before a tas

Special-Function Register Reset ValuesHigh-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement21REGISTERBIT 7 BIT 6 BIT 5 BIT 4 BIT 3

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement210ADDITIONAL FUNCTIONS AVAILABLE IN ROM VERSION 1.2.0If the ROM version (as

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement211info_convhexThis function converts 4-bit value into ASCII representation o

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement212arp_checkcacheThis function checks whether the system has an ARP cache ent

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement213task_suspend_ncThis function is similar to task_suspend, but it does not e

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement214ip_checkheader(IPv4 only) This function checks to see if the network stack

2. rom_redirect_init Copies the redirect call table from ROM to external memory 0100h–017Fh.3. ---- SETB EPFI instruction enables power-fail interrup

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplementASYNCHRONOUS TCP/IP MAINTENANCE FUNCTIONSThe default timer-interrupt handler

ROM REDIRECT FUNCTION TABLESince the socket interface is used by both NetBoot (from DS80C400 silicon software) and the user code (possibly running und

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplementROM REDIRECT FUNCTIONSThe usage of those ROM redirect functions not previousl

infosendcharThe infosendchar function sends a character to the serial port 0. The DS80C400 silicon software version of this function accesses theseria

Special-Function Register Reset Values (continued)High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement22REGISTERBIT 7 BIT 6 BIT 5

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplementTIMESLICE AND TASK SCHEDULER TIMINGThe task scheduler is primarily driven by

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplementREVISIONNUMBERREVISIONDATESECTIONNUMBERDESCRIP TIONPAGESCHANGED0 12/02 — Init

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement23REGISTERBIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0ADDRESSSADEN2 0 0 0

Special-Function RegistersThe DS80C400 has many unique features as compared to the standard 8052 microcontroller. These features are controlled by use

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement25SP.7–0Bits 7–0Stack pointer. This stack pointer identifies current location

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement26Data Pointer Select (DPS)ID1, ID0Bits 7–6TSLBit 5AIDBit 4ReservedBits 2, 1S

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement27Power Control (PCON)SMOD_0Bit 7SMOD0Bit 6OFDFBit 5OFDEBit 4GF1Bit 3GF0Bit 2

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement28Timer/Counter Control (TCON)TF1Bit 7TR1Bit 6TF0Bit 5TR0Bit 4IE1Bit 3IT1Bit

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement29Timer Mode Control (TMOD)7 6543210SFR 89h GATE C/T M1 M0 GATE C/T M1 M0RW-0

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement3Data Pointer Extended Register 1 (DPX1) . . . . . . . . . . . . . . . . . .

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement30Timer 0 LSB (TL0)Timer 1 LSB (TL1) Timer 0 MSB (TH0) Timer 1 MSB (TH1) TL0.

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement31Clock Control (CKCON)WD1, WD0Bits 7-6Watchdog timer mode select 1-0. These

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement32Port 1 (P1) 76543210SFR 90hP1.7INT5P1.6INT4P1.5INT3P1.4INT2P1.3TXD1P1.2RXD1

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement33External Interrupt Flag (EXIF)7 6543210SFR 91h IE5 IE4 IE3 IE2 CKRY RGMD RG

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement34Port 4 Control Register (P4CNT)76543210SFR 92h - - P4CNT.5 P4CNT.4 P4CNT.3

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement35Data Pointer Extended Register 0 (DPX)Data Pointer Extended Register 1 (DPX

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement36CAN 0 Receive Message Stored Register 0 (C0RMS0)7 6543210SFR 96h C0RMS0.7 C

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement37CAN 0 Receive Message Stored Register 1 (C0RMS1)76543210SFR 97h CORMS1.7 CO

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement38Serial Port 0 Control (SCON0)Serial Data Buffer 0 (SBUF0)7 6543210SFR 98h S

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement39Extended Stack Pointer Register (ESP)Address Page Register (AP)765 43210SFR

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement4CAN 0 Message Center 15 Control Register (C0M15C) . . . . . . . . . . . . .

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement40Address Control Register (ACON)7 6543210SFR 9Dh — — MROM BPME BROM SA AM1 A

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement41Programming AM1 and AM0 to 10 or 11 enables the fully contiguous 24-bit pro

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement42CAN 0 Transmit Message Acknowledgment Register 1 (C0TMA1)7 6543210SFR 9Fh —

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement43Port 5 (P5)Port 2 (P2)7 6543210SFR A0h A15/P2.7 A14/P2.6 A13/P2.5 A12/P2.4

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement44Port 5 Control Register (P5CNT)76543210SFR A2h — CAN0BA — — C0_I/O P5CNT.2

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement45CAN 0 Control Register (C0C)7 6543210SFR A3h ERIE STIE PDE SIESTA CRST AUTO

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement46CRSTBit 3AUTOBBit 2low-power mode. Setting SIESTA does not alter any CAN bl

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement47ERCSBit 1SWINTBit 0In the second case, consider a system with only two node

CAN 0 Status Register (C0S)High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement48C0S.7–0Bits 7-0BSSBit 7EC96/128Bit 6CAN 0 status

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement49WKSBit 5RXSBit 4TXSBit 3CAN 0 wake-up status. (Read only.) WKS = 0 indicate

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement5B Register (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement50ER2-0Bits 2-0CAN 0 bus error status 2-0. The ER2–ER0 bits indicate the firs

CAN 0 Interrupt Register (C0IR)High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement5176543210SFR A5h INTIN7 INTIN6 INTIN5 INTIN4

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement52Description:1A. STIE = 1 only (polling method: ETI = ERI 0) with no prior i

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement53General Issues:The INTIN vector value does not change when a new interrupt

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement54CAN 0 Receive-Error Register (C0RE)The following are the values of the INTI

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement55Interrupt Enable (IE)Slave Address Register 0 (SADDR0)SADDR0.7–0Bits 7–0Sla

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement56CAN 0 Message Center 1 Control Register (C0M1C)Slave Address Register 1 (SA

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement57EXTRQBit 3MTRQBit 2ROW/TIHBit 1External transmit request. (Read/clear only.

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement58DTUPBit 0If the message center being set up with WTOE = 1 was previously a

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement59CAN 0 Message Center 2 Control Register (C0M2C)CAN 0 Message Center 3 Contr

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement6Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement60Port 3 (P3)7 6543210SFR B0hP3.7RDP3.6WRP3.5T1P3.4T0P3.3INT1P3.2INT0P3.1TXD0

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement61Port 6 (P6) 7 6543210SFR B1hP6.7TXD2P6.6RXD2P6.5A21P6.4A20P6.3CE7P6.2CE6P6.

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement62Port 6 Control Register (P6CNT)7 6543210SFR B2h — — P6CNT.5 P6CNT.4 P6CNT.3

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement63Peripheral Chip-Enable Boundaries—DS80C400Peripheral Chip-Enable Boundaries

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement64CAN 0 Message Center 7 Control Register (C0M7C)CAN 0 Message Center 8 Contr

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement65Interrupt Priority (IP)76543210SFR B8h — PS1 PT2 PS0 PT1 PX1 PT0 PX0— RW-0

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement66Slave Address Mask Enable Register 1 (SADEN1)R = Unrestricted read, W = Unr

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement67CAN 0 Message Center 14 Control Register (C0M14C)R = Unrestricted read, C =

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement68Serial Data Buffer 1 (SBUF1)Power-Management Register (PMR)TB8_1Bit 3RB8_1B

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement69SWBBit 5CTMBit 44X/2XBit 3ALEOFFBit 2Bits 1-0Switchback enable. When set to

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement7ADDENDUM TO SECTION 15: BATTERY BACKUP 129Refer to the High-Speed Microcontr

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement70Status Register (STATUS)R = Unrestricted read, -n = Value after reset7 654

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement71Bit 4PDCE3Bit 3PDCE2Bit 2PDCE1Bit 1PDCE0Bit 0Reserved.Program/data chip ena

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement72Timer 2 Control (T2CON)R = Unrestricted read, W = Unrestricted write, -n =

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement73Timer 2 Mode (T2MOD)R = Unrestricted read, W = Unrestricted write, -n = Val

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement74Timer 2 LSB (TL2)R = Unrestricted read, W = Unrestricted write, -n = Value

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement75Program Status Word (PSW)R = Unrestricted read, W = Unrestricted write, -n

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement76Multiplier Control Register 0 (MCNT0)R = Unrestricted read, W = Unrestricte

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement77Multiplier Control Register 1 (MCNT1)R = Unrestricted read, W = Unrestricte

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement78A read pointer and a write pointer keep track of which of the four bytes is

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement797 6 5 4 3 2 1 0SFR D6h IRAMD PRAME — — PDCE7 PDCE6 PDCE5 PDCE4RT-* RT-* RT-

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement8CAN 0 Message Center y Format Register (C0MyF) . . . . . . . . . . . . . . .

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement80PDCE7Bit 3PDCE6Bit 2PDCE5Bit 1PDCE4Bit 0Program/data chip enable 7. PDCE7 p

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement81Memory Control Register 2 (MCON2)R = Unrestricted read, T = Timed-access wr

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement82Watchdog Control (WDCON)R = Unrestricted read, W = Unrestricted write, T =

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement8376543210SFR DAh BPA1.7 BPA1.6 BPA1.5 BPA1.4 BPA1.3 BPA1.2 BPA1.1 BPA1.0RW-0

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement847 6543210SFR E0h ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0RW-0 RW-0 R

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement857 6543210SFR E5h FPE RBF — BS4 BS3 BS2 BS1 BS0RT-0 R-1 RT-0 RT-0 RT-0 RT-0

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement8676543210SFR E7h BUSY EPMF TIF RIF BC3 BC2 BC1 BC0RW-0 RW-0 RW-0 RW-0 RW-0 R

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement8776543210SFR E8h EPMIE C0IE EAIE EWDI EWPI ES2 ET3 EX2-5RW-0 RW-0 RW-0 RW-0

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement8876543210SFR EDh DPX3.7 DPX3.6 DPX3.5 DPX3.4 DPX3.3 DPX3.2 DPX3.1 DPX3.0RW-0

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement897 6543210SFR EFhOWMDR.7OWMDR.6OWMDR.5OWMDR.4OWMDR.3OWMDR.2OWMDR.1OWMDR.0RW-

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement9Setting Up and Using the 1-Wire Master . . . . . . . . . . . . . . . . . .

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement9076543210SFR F5h DPH3.7 DPH3.6 DPH3.5 DPH3.4 DPH3.3 DPH3.2 DPH3.1 DPH3.0RW-0

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement9176543210SFR F7 — — — — V1PF V3PF SPTA2 SPRA2R-1 R-1 R-1 R-1 R-0 R-0 R-0 R-0

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement927 6543210SFR F9h P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0RW-1 RW-1 RW-1 RW-1

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement9376543210SFR FDh TF3 TR3 T3M SMOD_2 GATE C/T3 M1 M0RW-0 RW-0 RW-0 RW-0 RW-0

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement947 6543210SFR FEhSM0/FE_2SM1_2 SM2_2 REN_2 TB8_2 RB8_2 TI_2 RI_2RW-0 RW-0 RW

ADDENDUM TO SECTION 5: CPU TIMINGExternal Clock SourceThe DS80C400 supports a maximum operating frequency of 75MHz. However, when using an external cr

High-Speed Microcontroller User’sGuide: Network MicrocontrollerSupplement96Table 5-1. System Clock Configuration The system clock and machine cycle ra

ADDENDUM TO SECTION 6: MEMORY ACCESSInternal Program MemoryThe DS80C400 incorporates 64kB of on-chip ROM program memory. The 64kB block of memory is l

Internal Data MemoryDS80C400The DS80C400 incorporates 9472 bytes of internal SRAM memory, in addition to the standard 256-byte scratchpad memory. This

DS80C410/DS80C411Similar to the DS80C400, the DS80C410 and DS80C411 incorporate three internal SRAM memory blocks: a 1kB block usable as datamemory an