Maxim-integrated DS4830A Optical Microcontroller Uživatelský manuál Strana 123
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DS4830A User’s Guide
123
13.2 – 3-Wire Register Descriptions
The 3-Wire interface is controlled by two SFR registers. These are the 3-Wire Control Register TWR and Data and
Address Register DADDR. The TWR register configures and controls 3-Wire interface. The DADDR is used in 3-Wire
read and write operation. These registers are located at Module 2.
13.2.1 – 3-Wire Control Register (TWR)
Bit
7
6
5
4
3
2
1
0
Name
TWEN
TWCP[2:0]
TWIE
TWCSDIS
TWI
BUSY
Reset
0
0
0
0
0
0
0
0
Access
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BIT
NAME
DESCRIPTION
7
TWEN
3-Wire Enable. This bit enables the 3-Wire interface. When this bit is set to ‘1’, the
3-Wire interface is enabled. When this bit is cleared, the 3-Wire function is disabled.
6:4
TWCP[2:0]
3-Wire Clock Period. These bits are used for setting the 3-Wire MCL clock period.
TWCP[2:0]
MCL Clock Frequency (Period)
000
1 MHz (1000nSec)
001
714 KHz (1400nSec)
010
555 KHz (1800nSec)
011
454 KHz (2200nSec)
100
384 KHz (2600nSec)
101
333 KHz (3000nSec)
110
294 KHz (3400nSec)
111
263 KHz (3800nSec)
3
TWIE
3-Wire Interrupt Enable. Setting this bit to ‘1’ will enable an interrupt when the 3-
Wire data transfer is completed. Clearing this bit will disable the 3-Wire data transfer
complete interrupt.
2
TWCDIS
3-Wire Chip Select disable. Setting this bit to ‘1’, will disable the chip select and
the 3-
Wire Master interface will not control the chip select MCS during the
communication. In chip select disable mode, application program should control the
3-
Wire chip select by any GPIO. Clearing this bit will enable MCS as active chip
select and it is set to HIGH (See Figure 13-1) at start of 3-Wire data communication
and set to LOW once the 3-Wire data communication is completed.
1
TWI
3-Wire Interrupt. This bit is set to ‘1’ when data transfer is completed. This bit can
generate interrupt if TWIE bit is enabled. Once set, it should be cleared by software.
0
BUSY
3-Wire Busy. This bit is set to ‘1’ when data is written to the DADDR register and it
indicates
that the data transfer is in progress. This bit is reset to ‘0’ once the data
transfer is completed. This is also reset to zero when 3-Wire operation is disabled
(the TWEN bit is ‘0’). This is read only bit.
13.2.2 – Data and Address Register (DADDR)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
ADDR[15:9]
RWN
DATA[7:0]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
rw
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BIT
NAME
DESCRIPTION
15:9
ADDR[6:0]
3-Wire Address. These bits specify Slave device internal register address.
8
RWN
Read or Write Select. When this bit is set to ‘1’, the 3-Wire ‘Read’ operation is
performed. When this bit is ‘0’, the 3-Wire ‘Write’ operation is performed.
7:0
DATA[7:0]
3-Wire Data. During 3-Wire ‘Read’ operation (RWN = 1), the master writes the read
data from the 3-Wire bus at these bits. During 3-Wire ‘Write’ operation (RWN = 0),
the master sends data written at these bits on the 3-Wire bus.
Important Note: The entire DADDR register should be written at once instead of writing individual bits or
fields.
- DS4830A 1
- Optical Microcontroller 1
- User’s Guide 1
- Contents 2
- DS4830A User’s Guide 10
- SECTION 1 – OVERVIEW 11
- SECTION 2 – ARCHITECTURE 13
- 2.2 – Register Space 14
- 2.3 – Memory Types 15
- 2.5 – Data Alignment 22
- 2.6 – Reset Conditions 22
- 2.7 – Clock Generation 24
- INT_TRIG1 38
- INT_ALIGN 38
- BOOT_DIS 38
- SECTION 5 – INTERRUPTS 40
- 5.1 – Servicing Interrupts 41
- 6.1 – Detailed Description 45
- 6.3 – DAC Code Examples 47
- 7.1 – Detailed Description 48
- 7.3 – ADC Code Examples 63
- SECTION 8 – SAMPLE AND HOLD 65
- INT_TRIG_EN1 72
- INT_TRIG_EN0 72
- 9.1 – Detailed Description 73
- SECTION 10 – I 81
- 10.2 – I 90
- SECTION 11 – I 94
- C-COMPATIBLE SLAVE INTERFACE 94
- 11.1 – Detailed Description 95
- Detect START 96
- I2CSRI=1 96
- I2CBUS=1 96
- I2CBUSY=1 96
- 100 100
- 101 101
- 102 102
- 104 104
- 105 105
- 106 106
- 107 107
- 108 108
- 109 109
- 110 110
- SPI Slave 111
- 112 112
- 113 113
- 12.2 – SPI System Errors 113
- 114 114
- 115 115
- 116 116
- 117 117
- 118 118
- 119 119
- 120 120
- SECTION 13 – 3-WIRE 121
- 122 122
- 123 123
- Using PWMCN and 124
- 125 125
- 128 128
- 129 129
- 130 130
- 131 131
- 132 132
- 133 133
- 134 134
- FrequencyClockPWM 135
- FrequencyFrame 135
- 136 136
- 137 137
- 138 138
- 15.1 – Overview 138
- 140 140
- 141 141
- 142 142
- 143 143
- 16.1 – Detailed Description 143
- 144 144
- 145 145
- 146 146
- 147 147
- MULTIPLIER 148
- 149 149
- 150 150
- 151 151
- 152 152
- 153 153
- 154 154
- 155 155
- 156 156
- 19.1 - Overview 156
- 157 157
- 158 158
- 159 159
- 160 160
- 20.1 – TAP Controller 160
- 161 161
- 20.2 – TAP State Control 161
- 162 162
- 20.3 – Communication via TAP 162
- 163 163
- 164 164
- 165 165
- 166 166
- 167 167
- 168 168
- 169 169
- 170 170
- 21.2 – Debug Mode 170
- 171 171
- 172 172
- 173 173
- 174 174
- 175 175
- 176 176
- 177 177
- 178 178
- 179 179
- 22.1 – Detailed Description 179
- 180 180
- 181 181
- 182 182
- 22.2 – Bootloader Operation 182
- 183 183
- 184 184
- 22.3 – Bootloader Commands 184
- 185 185
- 186 186
- 187 187
- 188 188
- 189 189
- SECTION 23 – PROGRAMMING 190
- 191 191
- 192 192
- 193 193
- 194 194
- 195 195
- 196 196
- 197 197
- – Controlling Program Flow 197
- 198 198
- 199 199
- – Handling Interrupts 199
- 200 200
- – Accessing the Stack 200
- 201 201
- – Accessing Data Memory 201
- 202 202
- SECTION 24 – INSTRUCTION SET 203
- 204 204
- 205 205
- 206 206
- 207 207
- 208 208
- 209 209
- 210 210
- 211 211
- 212 212
- 213 213
- 214 214
- 215 215
- 216 216
- 217 217
- 218 218
- 219 219
- 220 220
- 221 221
- 222 222
- 223 223
- 224 224
- 225 225
- 226 226
- 227 227
- 228 228
- 229 229
- 230 230
- SECTION 25 – UTILITY ROM 231
- 232 232
- 233 233
- 234 234
- 235 235
- 236 236
- 237 237
- 25.4 Special Functions 237
- 238 238
- 25.5 – Utility ROM Examples 238
- SECTION 26 – MISCELLANEOUS 239
- 240 240
- 26.5 – Device Number and I 240
- C Bootloader Address Disable 240
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