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DS4830A User’s Guide
59
7.2.6.1 – ADC Configuration Register (ADDATA when ADCFG = 1 and ADCAVG = 0)
When ADCFG = 1 and ADCAVG = 0, writing to the ADDATA register writes to one of the configuration registers.
The configuration register written to is selected by the ADIDX[4:0] bits. The ADIDX[4:0] bits are automatically
incremented after a write to ADDATA. This allows consecutive writes of ADDATA to setup consecutive configuration
registers. The configuration registers are reset to ‘0’ on all forms of reset.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
-
ADGAIN[1:0]
ALT_LOC[4:0]
ADACQEN
ADALIGN
ADDIFF
ADCH[4:0]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
r
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
* When ADCFG = 1, unrestricted read, but can only be written to when ADCONV = 0.
BIT
NAME
DESCRIPTION
15
-
Reserved. The user should not write to this bit.
14:13
ADGAIN[1:0]
ADC Gain Select. This bit selects the ADC scale factor.
ADGAIN[1:0]
ADC SCALE
Full Scale (typ)
00
ADCG1
1.2V
01
ADCG2
0.6V
10
ADCG3
2.4V
11
ADCG4
6.55*
* When the ADCG4 select, the ADC input should not be above 3.6V. It is limited by VDD
operating range.
12:8
ALT_LOC[4:0]
Alternate location for conversion result. These bits specify the alternate location for
storing the ADC conversion result when LOC_OVR bit in the ADCN register is set to ‘1’.
7
ADACQEN
ADC Acquisition Extension Enable. Setting this bit to ‘1’ enables additional acquisition
time to be inserted prior to this conversion. Clearing this bit to ‘0’ disables the extended
acquisition time.
6
ADALIGN
ADC Data Alignment Select. This bit selects the ADC data alignment mode. Setting this
bit to ‘1’ returns ADC data left aligned in ADDATA [15:2] with ADDATA[1:0] zero padded.
Clearing this bit to ‘0’ returns ADC data in right aligned format in ADDATA[13:0] with
ADDATA[15:14] sign-extended by ADDATA[13].
5
ADDIFF
ADC Differential Mode Select. This bit selects the ADC conversion mode. When this bit
is set to ‘1’, the ADC conversion is in differential mode. When this bit is cleared to ‘0’, the
ADC conversion is performed in single-ended mode. In single-ended mode, the sample is
measured between the ADC Channel and ground.
4:0
ADCH[4:0]
ADC Channel Select. These bits select the input channel source for configuration of ADC
conversion.
ADCH [4:0]
ADDIFF = 0
ADDIFF=1
00000
ADC-S0
ADC-D0P- ADC-D0N
00001
ADC-S1
ADC-D1P- ADC-D1N
00010
ADC-S2
ADC-D2P- ADC-D2N
00011
ADC-S3
ADC-D3P- ADC-D3N
00100
ADC-S4
ADC-D4P- ADC-D4N
00101
ADC-S5
ADC-D5P- ADC-D5N
00110
ADC-S6
ADC-D6P- ADC-D6N
00111
ADC-S7
ADC-D7P- ADC-D7N
01000
ADC-S8
NOT VALID
01001
ADC-S9
NOT VALID
01010
ADC-S10
NOT VALID
01011
ADC-S11
NOT VALID
01100
ADC-S12
NOT VALID
01101
ADC-S13
NOT VALID
01110
ADC-S14
NOT VALID
01111
ADC-S15
NOT VALID
10000
ADC-REFINA
ADC-REFINA
10001
ADC-REFINB
ADC-REFINB
10010
VDD
VDD
10011
DAC_INT_REF
DAC_INT_REF
10100- 11000
NOT VALID
NOT VALID
11001
ADC OFFSET
ADC OFFSET
- DS4830A 1
- Optical Microcontroller 1
- User’s Guide 1
- Contents 2
- DS4830A User’s Guide 10
- SECTION 1 – OVERVIEW 11
- SECTION 2 – ARCHITECTURE 13
- 2.2 – Register Space 14
- 2.3 – Memory Types 15
- 2.5 – Data Alignment 22
- 2.6 – Reset Conditions 22
- 2.7 – Clock Generation 24
- INT_TRIG1 38
- INT_ALIGN 38
- BOOT_DIS 38
- SECTION 5 – INTERRUPTS 40
- 5.1 – Servicing Interrupts 41
- 6.1 – Detailed Description 45
- 6.3 – DAC Code Examples 47
- 7.1 – Detailed Description 48
- 7.3 – ADC Code Examples 63
- SECTION 8 – SAMPLE AND HOLD 65
- INT_TRIG_EN1 72
- INT_TRIG_EN0 72
- 9.1 – Detailed Description 73
- SECTION 10 – I 81
- 10.2 – I 90
- SECTION 11 – I 94
- C-COMPATIBLE SLAVE INTERFACE 94
- 11.1 – Detailed Description 95
- Detect START 96
- I2CSRI=1 96
- I2CBUS=1 96
- I2CBUSY=1 96
- 100 100
- 101 101
- 102 102
- 104 104
- 105 105
- 106 106
- 107 107
- 108 108
- 109 109
- 110 110
- SPI Slave 111
- 112 112
- 113 113
- 12.2 – SPI System Errors 113
- 114 114
- 115 115
- 116 116
- 117 117
- 118 118
- 119 119
- 120 120
- SECTION 13 – 3-WIRE 121
- 122 122
- 123 123
- Using PWMCN and 124
- 125 125
- 128 128
- 129 129
- 130 130
- 131 131
- 132 132
- 133 133
- 134 134
- FrequencyClockPWM 135
- FrequencyFrame 135
- 136 136
- 137 137
- 138 138
- 15.1 – Overview 138
- 140 140
- 141 141
- 142 142
- 143 143
- 16.1 – Detailed Description 143
- 144 144
- 145 145
- 146 146
- 147 147
- MULTIPLIER 148
- 149 149
- 150 150
- 151 151
- 152 152
- 153 153
- 154 154
- 155 155
- 156 156
- 19.1 - Overview 156
- 157 157
- 158 158
- 159 159
- 160 160
- 20.1 – TAP Controller 160
- 161 161
- 20.2 – TAP State Control 161
- 162 162
- 20.3 – Communication via TAP 162
- 163 163
- 164 164
- 165 165
- 166 166
- 167 167
- 168 168
- 169 169
- 170 170
- 21.2 – Debug Mode 170
- 171 171
- 172 172
- 173 173
- 174 174
- 175 175
- 176 176
- 177 177
- 178 178
- 179 179
- 22.1 – Detailed Description 179
- 180 180
- 181 181
- 182 182
- 22.2 – Bootloader Operation 182
- 183 183
- 184 184
- 22.3 – Bootloader Commands 184
- 185 185
- 186 186
- 187 187
- 188 188
- 189 189
- SECTION 23 – PROGRAMMING 190
- 191 191
- 192 192
- 193 193
- 194 194
- 195 195
- 196 196
- 197 197
- – Controlling Program Flow 197
- 198 198
- 199 199
- – Handling Interrupts 199
- 200 200
- – Accessing the Stack 200
- 201 201
- – Accessing Data Memory 201
- 202 202
- SECTION 24 – INSTRUCTION SET 203
- 204 204
- 205 205
- 206 206
- 207 207
- 208 208
- 209 209
- 210 210
- 211 211
- 212 212
- 213 213
- 214 214
- 215 215
- 216 216
- 217 217
- 218 218
- 219 219
- 220 220
- 221 221
- 222 222
- 223 223
- 224 224
- 225 225
- 226 226
- 227 227
- 228 228
- 229 229
- 230 230
- SECTION 25 – UTILITY ROM 231
- 232 232
- 233 233
- 234 234
- 235 235
- 236 236
- 237 237
- 25.4 Special Functions 237
- 238 238
- 25.5 – Utility ROM Examples 238
- SECTION 26 – MISCELLANEOUS 239
- 240 240
- 26.5 – Device Number and I 240
- C Bootloader Address Disable 240
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