Maxim-integrated MAXQ7666 manuály

Maxim integrated MAXQ7666 Uživatelský manuál (386 strany)

Značka: Maxim-integrated | Kategorie: Hardware | Velikost: 3.86 MB |

Angličtina

Tabulka s obsahem

Functional Diagrams

1

1.1 Overview

7

1.1.2 Instruction Set

8

1.1.4 Register Space

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1.2 Architecture

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1.2.1 Instruction Decoding

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1.2.2 Register Space

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1.2.3 Memory Organization

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1.2.3.2 Utility ROM

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1.2.3.3 Data Memory

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1.2.3.4 Stack Memory

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1.2.3.7 Data Alignment

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CDA0 = 1

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1.2.4 Interrupts

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1.3 Programming

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1.3.6.1 Sign Flag

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1.3.6.2 Zero Flag

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1.3.6.3 Equals Flag

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1.3.6.4 Carry Flag

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1.3.6.5 Overflow Flag

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1.3.7.2 Unconditional Jumps

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1.3.7.3 Conditional Jumps

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1.3.7.4 Calling Subroutines

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1.3.7.5 Looping Operations

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1.3.8 Handling Interrupts

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1.3.9 Accessing the Stack

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1.3.10 Accessing Data Memory

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1.4.19 General Register (GR)

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2.1 Architecture

75

2.3 Supply Configuration

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2.4 Linear Regulator

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2.5 Power-On Reset

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2.5.1 Power-Up Counter

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2.5.3 Reset Output

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2.7 Reset Mode

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2.7.2 External Reset

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2.7.3 Internal System Reset

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SECTION 3: ANALOG I/O MODULE

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3.1.1 Analog I/O Pins

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Register Name: ACNT

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ADCMX2 ADCMX1 FUNCTION

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1 1 Reserved

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Maxim Integrated

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Section 5

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Section 2

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Section 3.3.6

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Section 3.4

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Table 3-2. ADC Signals

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Section 3.3.10

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3.3.4 Unipolar/Bipolar

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3.3.5 Transfer Function

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Section 3.3.3

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Section 3.3.5

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3.3.7 Analog Input Protection

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3.3.8 ADC Clock

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3.3.9 Auto Shutdown Mode

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3.3.11 ADC Interrupts

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3.3.12 Using the ADC

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3.4 Temperature Sensor

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Sections 15

125

TEMPERATURE (°C)

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Section 3.4.2

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Table 3-12. DAC Signals

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3.5.4 DAC Power-Down

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3.5.5 Using the DAC

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LIST OF FIGURES

133

LIST OF TABLES

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4.1 Architecture

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4.2 CAN Controller Registers

136

4.3 CAN Operations

177

4.3.1.2 Remote Frame

180

4.3.1.3 Error Frame

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4.3.1.4 Overload Frame

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4.5 External Pins

182

4.7 CAN Interrupts

183

4.8.1 Message Center 15

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4.9.2 Receiving Data Messages

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4.15 Bit Timing

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4.16 CAN Bus Activity

197

5.1 Architecture

200

Section 3

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76543210

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Reset 0 0 1 0 0 0 0 1

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Access rw r r rw rw rw rw rw

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5.3 System Clock Generation

209

5.4 Watchdog Timer

215

5.5 Power Management Mode

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5.5.2 Switchback Mode

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5.5.3 Stop Mode

218

SECTION 6: SERIAL I/O MODULE

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6.1.1 UART Pins

223

6.2 UART Registers

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Serial Mode Definition

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— — — — — — —

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6.3 Modes of Operation

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6.3.3 UART Mode 2

230

6.3.4 UART Mode 3

230

6.4 Baud-Rate Generation

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6.4.4 Baud-Clock Generator

234

6.5 Framing Error Detection

235

7.1 Architecture

238

Compare Mode:

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Capture Mode:

244

7.2.3 Type 2 Reload Registers

248

7.3.3 16-Bit Counter

255

7.3.4 Dual 8-Bit Timers

256

7.4.3 Measure Period

259

8.1 Architecture

264

8.1.1 Port Pins

265

8.2 Port Registers

265

8.3 GPIO Operation

271

8.3.4 Port Pin Examples

273

9.1 Architecture

276

9.1.1 SPI Pins

277

9.2 SPI Peripheral Registers

277

9.3 SPI Operation

282

9.3.2 SPI Slave Operation

283

9.3.3 SPI Transfer Formats

284

9.4 SPI Transfer Baud Rates

285

9.5 SPI System Errors

285

9.6 SPI Interrupts

286

10.1 TAP Overview

289

10.2 Architecture

289

10.2.1 TAP Pins

290

10.3 TAP Interface Control

291

10.4 TAP Controller Operation

292

10.4.2 Run-Test-Idle

293

10.4.3 IR-Scan Sequence

293

10.4.5 Communication via TAP

294

11.1 Architecture

299

Section 12

303

Section 10

305

Section 1

305

11.3 Debug Engine Operation

306

11.3.2 Breakpoint Registers

308

11.3.3 Using Breakpoints

310

11.3.4 Debug Mode

311

11.3.5 Debug Mode Commands

311

11.3.8 Return

313

12.1 Bootstrap-Loader Mode

317

Section 11

318

Section 12.5

320

12.5 JTAG Bootloader Protocol

321

13.6 Operand Count Selection

335

13.8 Accessing the Multiplier

336

Acc.<b>

343

1000 1010 0001 1010

345

1101 1010 0010 1010

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0011 1100 ssss ssss

349

0111 1100 ssss ssss

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1111 1010 bbbb 1010

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1101 1010 0000 1010

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1110 1010 bbbb 1010

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1101 1010 0001 1010

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1ddd dddd 0bbb 0111

354

1ddd dddd 1bbb 0111

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1000 1010 1001 1010

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.<b>

356

1110 1100 0000 1101

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1001 1100 0000 1101

359

1101 1100 0000 1101

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1100 1100 0000 1101

359

1000 1100 1000 1101

360

1010 1100 1000 1101

360

1110 1100 1000 1101

360

1001 1100 1000 1101

361

1101 1100 1000 1101

361

1100 1100 1000 1101

361

1000 1010 0100 1010

362

1000 1010 0101 1010

362

1000 1010 1100 1010

363

1000 1010 1101 1010

363

1000 1010 0010 1010

364

1000 1010 0011 1010

364

1000 1010 0110 1010

364

1000 1010 1010 1010

365

1000 1010 1111 1010

365

1000 1010 1110 1010

366

1000 1010 1011 1010

366

1000 1010 0111 1010

368

1000 1010 1000 1010

368

1011 1010 bbbb 1010

369

WITH TYPE A FLASH)

371

15.2 Data Transfer Functions

372

TYPE F FLASH)

378

16.2 Data Transfer Functions

383

REVISION HISTORY

386

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