Maxim-integrated MAXQ Family Users Guide: MAXQ2010 Supplement Uživatelský manuál stáhnout pdf (Strana 21)

MAXQ Family User’s Guide:

MAXQ2010 Supplement

2-9

2.8 Reset Conditions

There are four possible reset sources for the MAXQ2010. While in the reset state, the enabled system clock oscillator

continues running, but no code execution occurs. Once the reset condition has been removed or has completed, code

execution resumes at address 8000h for all reset types.

Table 2-2. Interrupt Sources and Control Bits (continued)

INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG

External Interrupt 13 (P5.5) IM1 (IMR.1) EX13 (EIE1.5) IE13 (EIF1.5)

External Interrupt 14 (P5.6) IM1 (IMR.1) EX14 (EIE1.6) IE14 (EIF1.6)

External Interrupt 15 (P6.0) IM1 (IMR.1) EX15 (EIE2.0) IE15 (EIF2.0)

External Interrupt 16 (P6.1) IM1 (IMR.1) EX16 (EIE2.1) IE16 (EIF2.1)

External Interrupt 17 (P6.2) IM1 (IMR.1) EX17 (EIE2.2) IE17 (EIF2.2)

External Interrupt 18 (P6.3) IM1 (IMR.1) EX18 (EIE2.3) IE18 (EIF2.3)

External Interrupt 19 (P6.4) IM1 (IMR.1) EX19 (EIE2.4) IE19 (EIF2.4)

External Interrupt 20 (P6.5) IM1 (IMR.1) EX20 (EIE2.5) IE20 (EIF2.5)

External Interrupt 21 (P6.6) IM1 (IMR.1) EX21 (EIE2.6) IE21 (EIF2.6)

External Interrupt 22 (P6.7) IM1 (IMR.1) EX22 (EIE2.7) IE22 (EIF2.7)

Supply Voltage Monitor Interrupt IM1 (IMR.1) SVMIE (SVM.2) SVMI (SVM.3)

SPI Mode Fault Interrupt IM1 (IMR.1) ESPII (SPICF.7) MODF (SPICN.3)

SPI Write Collision Interrupt IM1 (IMR.1) ESPII (SPICF.7) WCOL (SPICN.4)

SPI Receive Overrun Interrupt IM1 (IMR.1) ESPII (SPICF.7) ROVR (SPICN.5)

SPI Transfer Complete Interrupt IM1 (IMR.1) ESPII (SPICF.7) SPIC (SPICN.6)

C START Condition Interrupt IM3 (IMR.3) I2CSRI (I2CST.0) I2CSRIE (I2CIE.0)

C Transmit Complete Interrupt IM3 (IMR.3) I2CTXI (I2CST.1) I2CTXIE (I2CIE.1)

C Receive Ready Interrupt IM3 (IMR.3) I2CRXI (I2CST.2) I2CRXIE (I2CIE.2)

C Clock Stretch Interrupt IM3 (IMR.3) I2CSTRI (I2CST.3) I2CSTRIE (I2CIE.3)

C Timeout Interrupt IM3 (IMR.3) I2CTOI (I2CST.4) I2CTOIE (I2CIE.4)

C Slave Address Match Interrupt IM3 (IMR.3) I2CAMI (I2CST.5) I2CAMIE (I2CIE.5)

C Arbitration Loss Interrupt IM3 (IMR.3) I2CALI (I2CST.6) I2CALIE (I2CIE.6)

C NACK Interrupt IM3 (IMR.3) I2CNACKI (I2CST.7) I2CNACKIE (I2CIE.7)

C General Call Address Interrupt IM3 (IMR.3) I2CGCI (I2CST.8) I2CGCIE (I2CIE.8)

C Receiver Overrun Interrupt IM3 (IMR.3) I2CROI (I2CST.9) I2CROIE (I2CIE.9)

C STOP Condition Interrupt IM3 (IMR.3) I2CSPI (I2CST.11) I2CSPIE (I2CIE.11)

Serial Port 0 Receive IM3 (IMR.3) ESI (SMD0.2) RI (SCON0.0)

Serial Port 0 Transmit IM3 (IMR.3) ESI (SMD0.2) TI (SCON0.1)

Serial Port 1 Receive IM3 (IMR.3) ESI (SMD1.2) RI (SCON1.0)

Serial Port 1 Transmit IM3 (IMR.3) ESI (SMD1.2) TI (SCON1.1)

ADC Data Available Interrupt IM4 (IMR.4) ADDAIE (ADCN.5) ADDAI (ADST.5)

Type B Timer 0—External Trigger IM4 (IMR.4) EXFB (TB0CN.6) ETB (TB0CN.1)

Type B Timer 0—Overflow IM4 (IMR.4) TFB (TB0CN.7) ETB (TB0CN.1)

Type B Timer 1—External Trigger IM4 (IMR.4) EXFB (TB1CN.6) ETB (TB1CN.1)

Type B Timer 1—Overflow IM4 (IMR.4) TFB (TB1CN.7) ETB (TB1CN.1)

Type B Timer 2—External Trigger IM4 (IMR.4) EXFB (TB2CN.6) ETB (TB2CN.1)

Type B Timer 2—Overflow IM4 (IMR.4) TFB (TB2CN.7) ETB (TB2CN.1)

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 146 147

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