Maxim-integrated MAXQ7666 Uživatelský manuál Strana 315
- Strana / 386
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
11.3.10.3 Data Memory Write Command
When invoking this command, ICDA should be set to the word address of the location to write to, and ICDD should be set to the data
word to write. The input address must be based on the utility ROM memory map, as shown in Section 1.
11.3.10.4 Program Stack Read Command
When invoking this command, ICDA should be set to the address of the starting stack location (value of SP) to read from, and ICDD
should be set to the number of words. The address given in ICDA is the highest value that will be used, as words are popped off the
stack and returned in descending order. Stack words returned by this command are output LSB first.
11.3.10.5 Read Register Map Command
This command outputs all peripheral registers in the range M0[00h] to M5[0Dh], along with a fixed set of system registers. The follow-
ing formatting rules apply to the returned data.
• System registers are output as 8-bit or 16-bit, least significant byte first.
• All peripheral registers are output as 16-bit, least significant byte first. The top byte of 8-bit registers is returned as 00h.
• Non-implemented peripheral registers in the range M0[00h] to M5[0Dh] are returned as 0000h.
• The value of SBUF0, SPIB, C0S, C0DB, C0RMS, C0TMA, and ASR are not read, and this register is returned as 0000h.
The first byte output by this command is the value 174 (AEh), which represents the number of peripheral registers output. Table 11-3
lists the remaining 412 bytes output by this command.
MAXQ7665/MAXQ7666 User’s Guide
11-19
x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x
PO0 00 00 00 00 EIF0 00 00 00 00 00 00 00 00
1x
PI0 00 00 00 00 EIE0 00 00 00 00 00 00 00 00
2x
PD0 00 00 00 00 EIES0 00 00 00 00 00 00 00 00
3x
00 00 00 00 00 00 00 00 00 00 SCON0 SMD0 PR0
4x
MCNT MA MB MC2 MC1 MC0 00 00 SPICN
5x
SPICF SPICK FCNTL FDATA MC1R MC0R 00 00 00 00
6x
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
7x
00 00 00 00 00 00 00 00 FADDR 00 00 00 00 00 00
8x
T2CNA0 T2H0 T2RH0 T2CH0 T2CNA1 T2H1 T2RH1 T2CH1
9x
T2CNB0 T2V0 T2R0 T2C0 T2CNB1 T2V1 T2R1 T2C1
Ax
T2CFG0 T2CFG1 00 00 00 00 00 00 00 00 00 00 00 00
Bx
ICDT0 ICDT1 00 ICDC 00 ICDF 00 ICDB ICDA ICDD TM
Cx
T2CNA2 T2H2 T2RH2 T2CH2 00 00 00 00 00 00 00 00
Dx
T2CNB2 T2V2 T2R2 T2C2 00 00 00 00 00 00 00 00
Ex
T2CFG2 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Fx
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
10x
C0C 00 00 C0IR C0TE C0RE COR C0DP 00 00
11x
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
12x
00 00 C0M1C C0M2C C0M3C C0M4C C0M5C C0M6C C0M7C
13x
C0M8C C0M9C C0M10C C0M11C C0M12C C0M13C C0M14C C0M15C
14x
VMC APE ACNT DCNT DACI 00 00 DACO 00 00
15x
ADCD TSO AIE 00 00 OSCC OTP AP APC PSF IC
16x
IMR SC IIR CKCN WDCN 00 A[0] A[1] A[2] A[3] A[4]
17x
A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12]
18x
A[13] A[14] A[15] IP SP+1 IV LC[0] LC[1]
19x
OFFS DPC GR BP DP[0] DP[1]
Table 11-3. Output from DebugReadMap Command
Maxim Integrated
- Functional Diagrams 1
- 1.1 Overview 7
- 1.1.2 Instruction Set 8
- 1.1.4 Register Space 8
- 1.2 Architecture 9
- 1.2.1 Instruction Decoding 10
- 1.2.2 Register Space 11
- 1.2.3 Memory Organization 13
- 1.2.3.2 Utility ROM 16
- 1.2.3.3 Data Memory 16
- 1.2.3.4 Stack Memory 17
- 1.2.3.7 Data Alignment 19
- CDA0 = 1 21
- 1.2.4 Interrupts 25
- 1.3 Programming 31
- 1.3.6.1 Sign Flag 37
- 1.3.6.2 Zero Flag 38
- 1.3.6.3 Equals Flag 38
- 1.3.6.4 Carry Flag 38
- 1.3.6.5 Overflow Flag 39
- 1.3.7.2 Unconditional Jumps 39
- 1.3.7.3 Conditional Jumps 40
- 1.3.7.4 Calling Subroutines 40
- 1.3.7.5 Looping Operations 40
- 1.3.8 Handling Interrupts 41
- 1.3.9 Accessing the Stack 42
- 1.3.10 Accessing Data Memory 43
- 1.4.19 General Register (GR) 59
- 2.1 Architecture 75
- 2.3 Supply Configuration 83
- 2.4 Linear Regulator 84
- 2.5 Power-On Reset 84
- 2.5.1 Power-Up Counter 85
- 2.5.3 Reset Output 87
- 2.7 Reset Mode 89
- 2.7.2 External Reset 90
- 2.7.3 Internal System Reset 90
- SECTION 3: ANALOG I/O MODULE 91
- 3.1.1 Analog I/O Pins 96
- Register Name: ACNT 98
- ADCMX2 ADCMX1 FUNCTION 99
- 1 1 Reserved 99
- Maxim Integrated 100
- Section 5 104
- Section 2 104
- Section 3.3.6 107
- Section 3.4 107
- Table 3-2. ADC Signals 108
- Section 3.3.10 110
- 3.3.4 Unipolar/Bipolar 111
- 3.3.5 Transfer Function 112
- Section 3.3.3 115
- Section 3.3.5 115
- 3.3.7 Analog Input Protection 116
- 3.3.8 ADC Clock 117
- 3.3.9 Auto Shutdown Mode 117
- 3.3.11 ADC Interrupts 122
- 3.3.12 Using the ADC 123
- 3.4 Temperature Sensor 124
- Sections 15 125
- TEMPERATURE (°C) 126
- Section 3.4.2 127
- Table 3-12. DAC Signals 128
- 3.5.4 DAC Power-Down 130
- 3.5.5 Using the DAC 130
- LIST OF FIGURES 133
- LIST OF TABLES 133
- 4.1 Architecture 134
- 4.2 CAN Controller Registers 136
- 4.3 CAN Operations 177
- 4.3.1.2 Remote Frame 180
- 4.3.1.3 Error Frame 181
- 4.3.1.4 Overload Frame 181
- 4.5 External Pins 182
- 4.7 CAN Interrupts 183
- 4.8.1 Message Center 15 185
- 4.9.2 Receiving Data Messages 186
- 4.15 Bit Timing 194
- 4.16 CAN Bus Activity 197
- 5.1 Architecture 200
- Section 3 204
- 76543210 205
- Reset 0 0 1 0 0 0 0 1 205
- Access rw r r rw rw rw rw rw 205
- 5.3 System Clock Generation 209
- 5.4 Watchdog Timer 215
- 5.5 Power Management Mode 217
- 5.5.2 Switchback Mode 218
- 5.5.3 Stop Mode 218
- SECTION 6: SERIAL I/O MODULE 219
- 6.1.1 UART Pins 223
- 6.2 UART Registers 223
- Serial Mode Definition 224
- — — — — — — — 226
- 6.3 Modes of Operation 227
- 6.3.3 UART Mode 2 230
- 6.3.4 UART Mode 3 230
- 6.4 Baud-Rate Generation 233
- 6.4.4 Baud-Clock Generator 234
- 6.5 Framing Error Detection 235
- 7.1 Architecture 238
- Compare Mode: 244
- Capture Mode: 244
- 7.2.3 Type 2 Reload Registers 248
- 7.3.3 16-Bit Counter 255
- 7.3.4 Dual 8-Bit Timers 256
- 7.4.3 Measure Period 259
- 8.1 Architecture 264
- 8.1.1 Port Pins 265
- 8.2 Port Registers 265
- 8.3 GPIO Operation 271
- 8.3.4 Port Pin Examples 273
- 9.1 Architecture 276
- 9.1.1 SPI Pins 277
- 9.2 SPI Peripheral Registers 277
- 9.3 SPI Operation 282
- 9.3.2 SPI Slave Operation 283
- 9.3.3 SPI Transfer Formats 284
- 9.4 SPI Transfer Baud Rates 285
- 9.5 SPI System Errors 285
- 9.6 SPI Interrupts 286
- 10.1 TAP Overview 289
- 10.2 Architecture 289
- 10.2.1 TAP Pins 290
- 10.3 TAP Interface Control 291
- 10.4 TAP Controller Operation 292
- 10.4.2 Run-Test-Idle 293
- 10.4.3 IR-Scan Sequence 293
- 10.4.5 Communication via TAP 294
- 11.1 Architecture 299
- Section 12 303
- Section 10 305
- Section 1 305
- 11.3 Debug Engine Operation 306
- 11.3.2 Breakpoint Registers 308
- 11.3.3 Using Breakpoints 310
- 11.3.4 Debug Mode 311
- 11.3.5 Debug Mode Commands 311
- 11.3.8 Return 313
- 12.1 Bootstrap-Loader Mode 317
- Section 11 318
- Section 12.5 320
- 12.5 JTAG Bootloader Protocol 321
- 13.6 Operand Count Selection 335
- 13.8 Accessing the Multiplier 336
- Acc.<b> 343
- 1000 1010 0001 1010 345
- 1101 1010 0010 1010 346
- 0011 1100 ssss ssss 349
- 0111 1100 ssss ssss 349
- 1111 1010 bbbb 1010 352
- 1101 1010 0000 1010 353
- 1110 1010 bbbb 1010 353
- 1101 1010 0001 1010 354
- 1ddd dddd 0bbb 0111 354
- 1ddd dddd 1bbb 0111 354
- 1000 1010 1001 1010 355
- .<b> 356
- 1110 1100 0000 1101 359
- 1001 1100 0000 1101 359
- 1101 1100 0000 1101 359
- 1100 1100 0000 1101 359
- 1000 1100 1000 1101 360
- 1010 1100 1000 1101 360
- 1110 1100 1000 1101 360
- 1001 1100 1000 1101 361
- 1101 1100 1000 1101 361
- 1100 1100 1000 1101 361
- 1000 1010 0100 1010 362
- 1000 1010 0101 1010 362
- 1000 1010 1100 1010 363
- 1000 1010 1101 1010 363
- 1000 1010 0010 1010 364
- 1000 1010 0011 1010 364
- 1000 1010 0110 1010 364
- 1000 1010 1010 1010 365
- 1000 1010 1111 1010 365
- 1000 1010 1110 1010 366
- 1000 1010 1011 1010 366
- 1000 1010 0111 1010 368
- 1000 1010 1000 1010 368
- 1011 1010 bbbb 1010 369
- WITH TYPE A FLASH) 371
- 15.2 Data Transfer Functions 372
- TYPE F FLASH) 378
- 16.2 Data Transfer Functions 383
- REVISION HISTORY 386
Související produkty a manuály pro Hardware Maxim-integrated MAXQ7666
Hardware Maxim-integrated MAXQ7667 Uživatelský manuál
(347 stránky)
(347 stránky)
Hardware Maxim-integrated MAXQ Family Users Guide: MAXQ8913 Supplement Uživatelský manuál
(114 stránky)
(114 stránky)
Hardware Maxim-integrated High-Speed Microcontroller Users Guide: DS80C390 S Uživatelský manuál
(158 stránky)
(158 stránky)
Hardware Maxim-integrated High-Speed Microcontroller Users Guide: Network Mi Uživatelský manuál
(221 stránky)
(221 stránky)
Hardware Maxim-integrated MAX31782 Uživatelský manuál
(223 stránky)
(223 stránky)
Hardware Maxim-integrated 78M6631 Uživatelský manuál
(32 stránky)
(32 stránky)
© 2020, manymanuals.cz. Všechna práva vyhrazena. | 0.090 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentáře k této Příručce