Maxim-integrated MAXQ7667 Uživatelský manuál stáhnout pdf (Strana 11)

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___________________________________________________________________________________________________________ 2-6

MAXQ7667 User’s Guide

2.2 Architecture

The MAXQ7667 architecture is designed to be modular and expandable. Top-level instruction decoding is extremely simple and based

on transfers to and from registers. The registers are organized into functional modules, which are in turn divided into the system reg-

ister and peripheral register groups. Figure 2-2 illustrates the modular architecture.

SYSTEM MODULES/

REGISTERS



PERIPHERAL MODULES/REGISTERS



DATA 

MEMORY

dst

STACK

MEMORY

CKCN

WDCN

ADDRESS

GENERATION

LOOP COUNTERS

LC[η]

IIR

IMR

INTERRUPT

LOGIC

CLOCK CONTROL,

WATCHDOG TIMER

AND POWER MONITOR

BOOLEAN

VARIABLE

MANIPULATION

ACCUMULATORS

(16)

APC

PSF

INSTRUCTION

DECODE



(SRC, DST TRANSPORT

DETERMINATION)

MUX

DATA POINTERS

DP[0], DP[1]

FP =

(BP + OFFS)

DPC

MEMORY MANAGEMENT

UNIT (MMU)

PROGRAM

MEMORY



src

dst

src

GENERAL- 

PURPOSE

I/O

TIMERS/

COUNTERS

UART

(LIN)

SPI

ANALOG

HARDWARE

MULTIPLIER

JTAG

DEBUG

ENGINE

SCHEDULE

TIMER

CLOCK

ULTRASONIC

SOUND

MEASUREMENT

Figure 2-2. MAXQ7667 Transport-Triggered Architecture

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 346 347

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