Maxim-integrated MAXQ7667 Uživatelský manuál stáhnout pdf (Strana 146)

8.3.15 Serial Address Mask Register (UART) (SADEN)

egister Name:

ADEN

Bits 7 to 0: Serial Address Mask Register 7:0 (SADEN[7:0]).

In legacy UART mode, this register can be written by the host to con-

figure the address mask for the peripheral in one of the 9-bit communication modes (mode 2 or mode 3). This register serves no func-

tion if the peripheral is configured for LIN master or LIN slave mode.

8.3.16 Bit Timing Register (UART) (BT)

Bits 15 to 0: Bit Timing Register 15:0 (BT[15:0]).

In legacy UART mode, the host initializes this register to configure the baud-rate

generator for the cor

ect communication speed. In LIN mode, the host writes this register during system initialization to configur

e the

nor

mal bit timing on the bus. Hardwar

e updates this register with the measur

ed bit timing whenever a break/sync sequence is detect-

ed. The host can always r

ead this register to determine the measured bit timing for the most recent LIN frame.

In legacy UART mode this register is the phase register.

Bits 15 to 0: Phase Register 15:0 (BT[15:0]). This r

egister is used to load and read the 16-bit value in the phase register that deter-

mines the baud rate for the serial port 0.

__________________________________________________________________________________________________________ 8-16

MAXQ7667 User’s Guide

r = read, w = write

Note: SADEN is cleared to 00h on all forms of reset.

it #

6543210

Name SADEN7 SADEN6 SADEN5 SADEN4 SADEN3 SADEN2 SADEN1 SADEN0

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

r = r

ead, w = write

Note: BT is clear

ed to 0000h on all for

ms of r

eset.

Bit #

15 14 13 12 11 10 98

Name BT15 BT14 BT13 BT12 BT11 BT10 BT9 BT8

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

Bit #

76543210

Name BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

1 2 ... 141 142 143 144 145 146 147 148 149 150 151 ... 346 347

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