Maxim-integrated MAXQ7667 Uživatelský manuál stáhnout pdf (Strana 196)

11-7 __________________________________________________________________________________________________________

MAXQ7667 User’s Guide

When the parallel instruction register (IR[2:0]) is updated, the TAP controller decodes the instruction and performs any necessary oper-

ations, including activation of the data shift register to be used for the particular instruction during data register shift sequences (DR-

can). The length of the activated shift register depends upon the value loaded to the instruction register (IR[2:0]). The supported

instruction register encodings and associated data-register selections are shown in Table 11-3.

The extest (IR[2:0] = 000b) and sample/preload (IR[2:0] = 001b) instructions are mandated by the JTAG standard; however, the

AXQ7667 does not make use of these instructions. These instructions are treated as no operations and may be entered into the instruc-

tion register without affecting the on-chip system logic or pins and does not change the existing serial data register selection between TDI

and TDO.

he bypass (IR[2:0] = 011b, 101b, or 111b) instruction is also mandated by the JTAG standard. The bypass instruction is fully imple-

mented by the MAXQ7667 to provide a minimum length serial data path between the TDI and the TDO pins. This is accomplished by

providing a single-cell bypass shift register. When the instruction register is updated with the bypass instruction, a single bypass regis-

ter bit is connected serially between TDI and TDO in the shift-DR state. The instruction register automatically defaults to the bypass

instruction when the TAP is in the test-logic-reset state. The bypass instruction has no effect on the operation of the on-chip system logic.

The debug (IR[2:0] = 010b) and system programming (IR[2:0] = 100b) instructions are private instructions that are intended solely for

in-circuit debug and in-system programming operations, respectively. If the instruction register is updated with the debug instruction,

a 10-bit serial shift register is formed between the TDI and TDO pins in the shift-DR state. If the system programming instruction is

entered into the instruction register (IR[2:0]), a 3-bit serial data shift register is formed between the TDI and TDO pins in the shift-DR

state.

Instruction register (IR[2:0]) settings other than those listed and previously described are reserved for internal use. As can be seen in

Figure 11-1, the instruction register serves to select the length of the serial data register between TDI and TDO during the shift-DR state.

*Also supports bootloader functions in the MAXQ7667.

**Provides information about programming source and enables the MAXQ7667 for programming.

11.4.5 DR-Scan Sequence

Once the instruction r

egister has been configured, using the IR-scan sequence, to a desir

ed state (mode), transactions ar

e per

for

med

via a data shift r

egister associated with that mode (as shown in T

able 11-3). These data transactions ar

e executed serially in a manner

analogous to the process used to load the instruction register. The transactions are grouped in the TAP controller state sequence start-

ing from the select-DR-scan state. In the TAP controller state sequence, the shift-DR state allows internal data to be shifted out through

the TDO pin while the exter

nal data is shifted in simultaneously via the TDI pin. Once a complete data pattern is shifted in, input data

can be latched into the parallel buf

fer of the selected r

egister on the falling edge of TCK in the update-DR state. On the same TCK

falling edge, in the update-DR state, the internal parallel buffer is loaded to the data shift register for output. This shift-DR/update-DR

process serves as the basis for passing information between the external host and the MAXQ7667. These data register transactions

occur in the data register portion of the TAP controller state sequence diagram and have no effect on the instruction register.

Table 11-3. Instruction Register Commands

IR[2:0] INSTR U C TION FU N C TION

SERIAL DA T A SH IFT

0 0

0 Extest No operation U nchanged ( retain previous selection)

0 0

1 Sa mple/Preload No operation Unchanged ( retain previous selection)

0 1

0 Debug In-circuit debug mode* 10-bit shift register

0 1

1 Bypass No operation (default) 1-bit shift register

1 0

0 System P rog ramm ing Bootstrap function** 3-bit shift register

1 0

1 Bypass No operation (default) 1-bit shift register

1 1

0 Reserved

1 1

1 Bypass N o operation (default) 1-bit shift register

1 2 ... 191 192 193 194 195 196 197 198 199 200 201 ... 346 347

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