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MAXQ7667 User’s Guide
Changing XTRC from 1 to 0 selects the internal RC oscillator as the system clock source. If the RC oscillator is already turned on, then
the switch to the RC clock is instantaneous. If the RC oscillator is turned off, then it takes four RC clock periods to turn on the oscilla-
t
or and make the switch.
Bit 6: Reserved. Read returns 0.
B
it 5: RC Oscillator Mode (RCMD).
T
his read-only bit reflects the selection of clock source. RCMD = 1 indicates the RC oscillator is
providing the system clock. RCMD = 0 indicates the external crystal is providing the system clock. Note that although RCMD is cleared
to 0 on all forms of reset, the RC clock is the default clock source so RCMD will normally be set to 1 shortly after the design starts to
clock.
Bit 4: Stop Mode Select (STOP). Setting this bit to 1 stops program execution and commences low-power operation. This bit is cleared
by a reset or any of the enabled external interrupts. Setting and resetting the STOP bit does not change the system clock-divide ratio.
Bit 3: Switchback Enable (SWB). When set to 1, SWB allows mask-enabled external interrupts as well as enabled serial port receive
functions to reset the PMME bit from 1 to 0, and allows the processor to switch back to the original system frequency as selected by
the CD1 and CD0 bits. When SWB is cleared to 0, switchback mode is disabled.
Conditions that trigger switchback include the following:
• The detection of a selected edge transaction on any of the external interrupts when the respective pin has been programmed
and enabled to issue an interrupt. Note that the switchback interrupt relationship requires that the respective external interrupt
source be allowed to actually generate an interrupt, before the switchback will actually occur.
• Activity on the SPI interface (when enabled). The switchback is independent of the SPI interrupt relationship.
• Activity on the UART interface (when enabled). The switchback is independent of the UART interrupt relationship.
• Entry into active debug mode either by a breakpoint match or issuance of the debug command.
Bit 2: Power Management Mode Enable (PMME). The PMME and CD[1:0] control bits select the divide ratio of the system clock from
a clock source.
PMME C D1 CD0 C LOC K - D IVIDE RA TIO
0 0 0 Div i de by 1 (default)
0 0 1 Div i de by 2 (unavailab le)
0 1 0 Div i de by 4 (unavailab le)
0 1 1 Div i de by 8 (unavailab le)
1 0 0 D ivi de by 256, Sw itchback to Div i de by 1 (unavailable)
1 0 1 D ivi de by 256, Sw itchback to Div i de by 2 (unavailable)
1 1 0 D ivi de by 256, Sw itchback to Div i de by 4 (unavailable)
1 1 1 D ivi de by 256, Sw itchback to Div i de by 8 (unavailable)
Bits 1 and 0: Clock Divide Control Bits 1 and 0 (CD[1:0])
(114 stránky)
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